DesiJ – A Tool for STG Decomposition

STG Decomposition and Its Correctness∗

The behaviour of asynchronous control circuits can be specified with Signal Transition Graphs (STGs), i.e. Petri nets where transitions are labelled with rising and falling edges of circuit signals. Speed independent (SI) circuits (an important and robust subclass of asynchronous circuits) can be synthesized from STGs with tools like PETRIFY [3] and PUNF&MPSAT [6]. For this purpose, PETRIFY bui...

STG-Level Decomposition and Resynthesis of Speed-Independent Circuits

This paper presents a time-efficient method for the decomposition and resynthesis of speed-independent (SI) circuits. Given the specification of an SI circuit, our method first generates its standard C implementation. Then, the combinational decomposition is performed to decompose each high-fanin gate that does not exist in the gate library into some available low-fanin gates. The time efficien...

Petri Nets 2000 Conference

CASCADE is a tool kernel that supports the synthesis of asynchronous controllers. It uses a generalized STG (an interpreted Petri net) as a uni ed design entry and allows the designer to choose between several appropriate design methods. It then transforms the initial speci cation into the design entry required by the chosen style, and interfaces with existing synthesis tools (petrify for SI ci...

COMPUTING SCIENCE Logic Decomposition of Asynchronous Circuits Using STG Unfoldings

A technique for logic decomposition of asynchronous circuits which works on STG unfolding prefixes rather than state graphs is proposed. It retains all the advantages of the state space based approach, such as the possibility of multiway acknowledgement, latch utilisation and highly optimised circuits. Moreover, it significantly alleviates the state space explosion, and thus has superior memory...

STG Decomposition: Avoiding Irreducible CSC Conflicts by Internal Communication